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Page history last edited by erik.seligman@... 13 years, 11 months ago

 
SystemVerilog Assertions Committee Home Page

 

 

Note:  In 2010, we have moved current activities onto an IEEE-hosted wiki.  Please visit that page for current info: 

http://www.eda.org/twiki/bin/view.cgi/P1800/SystemVerilogAssertionCommittee

 

 

Old Content

 

Charter

The SV-AC is the technical subcommittee of the IEEE P1800 Working Group that is tasked with maintaining and extending the assertion support within the SystemVerilog language.

 

 

Patent Policy

 

Organization

 

Special Committee

 

Active Email Discussions:

The work is almost done for the 2009 PAR; review is in progress of the final pre-release draft, Draft 7. See full discussion details in email archive. (Scroll to bottom!)

 

Meeting and Status Information

  • The committee work is complete for 2008, except for review of Draft 7 which is in progress.

 

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To subscribe, please send an email to mailto:majordomo@eda.org with the following in the body of the email:

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Web Page Info

  • It's a wiki, so don't be afraid to edit a page or add a subpage if you have more info for the committee.
  • Feel free to email erik.seligman@intel.com with any questions about how to use or edit this wiki.
  • Note: while this page supports file attachments, our free account has limited space. So if you have a file to attach, the preferred method is to attach a file to your Mantis ticket (which is on a separate system) and link from here, rather than attaching files directly here.

 

Last Meeting Minutes (2008-09-22):

Minutes of IEEE P1800 SV-AC meeting #2007-58

Written by: Dmitry Korchemny

 

Date: 2008-09-22

Time: 16:00 UTC (9:00 PDT)

 

Dial-in information:


 

Toll number: +1 916-356-2663

Toll free number (US): 888-875-9370 (U.S. toll-free)

Bridge: 3, Passcode: 2251581

 

 

Attendance Record:


Legend:

x = attended

- = missed

r = represented

. = not yet a member

v = valid voter (2 out of last 3 or 3/4 overall)

n = not a valid voter

t = chair eligible to vote only to make or break a tie

 

New PAR, attendance re-initialized on 2006-08-22:

 

vx-xx--x--xxxxxxxxx-xxxxxxxxxxxxxxxxxxxxxxxx-xxxxxxxxxxxxxxxxxxxxxxxx-xx Doron Bustan (Intel)

v----xx-xxxx-xxxxxxxxxxxxxxx--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx-x Eduard Cerny (Synopsys)

n--------------------------------------------x-xxx---------x-x-xxx-x---x Surrendra Dudani (Synopsys)

v--xxxxxx-xxxxxxxxxxx-xxxxxxxxx-xxxxxx-xxxxxxxxx-xx-xxxxx-xxx-xxx------- Yaniv Fais (Freescale)

vx---xxxxxxxxxxxxxxxxxxxxxx--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx John Havlicek (Freescale)

txxxxxxx-xxxxx-xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxrxxxxxxxxxxxxx-xxx Dmitry Korchemny (Intel – Chair)

n--x-----xxx--xx-x-xxxxxxxxx-xxxxxxxxx-xxx-x--xx--xxxxx----------xx-xxxx Manisha Kulshrestha (Mentor Graphics)

n-------------------x-x------------------------------------------------- Ah-Lam Lee (Qualcomm)

n----------------------------------------------------xxxxx-------x-xx-x- Jiang Long (Mentor Graphics)

n[-----x-xx-x--------------------x------------x--xxx.....................] Joseph Lu (Altera)

n[-----------------x-x--xxxxxxxxxxxxxxxxxxx..............................] Johan Martensson (Jasper)

n-------------------------------------------------x--x-xx--xx-xxxxxxx-x- Hillel Miller (Freescale)

vxx-xxxxxxxx-xxxxxxxxxxxxxxx-xxxx-xxxxxxxxxxxxxxxxxxx-xxxxxxxx-xxxxxxxxx Lisa Piper (Cadence)

v[xxxxxxxxxx-xxxxxx-xxxxxxxxxx-x-x-xx-xxxxxxx-x-xxxxx-x..................] Erik Seligman (Intel)

n-----------------------------x-x----x--------xxxx-----xxxx-xx---------- Tej Singh (Mentor Graphics)

vxxx-xx-xxxx-x-x-x-xxx-xxxxxx-x-xxxxxx--xxxxxxxx-xxxxxxxxxxxxxxxxxxxxxxx Bassam Tabbara (Synopsys)

v[-xxxxxxxxxxxxxxxxxxxxxxxxxxxxx-xxxxxxxxxxxxx-xxxxxxxxxx...............] Tom Thatcher (Sun Microsystems – Co-Chair)

|------------------------------------------------------ attendance on 2008-09-22

|-------------------------------------------------------- voting eligibility on 2008-09-22

 

Agenda:


 

- Reminder of IEEE patent policy.

See: http://standards.ieee.org/board/pat/pat-slideset.ppt

 

- Draft7 review.

 

  • Mantis implementation review.

All: review the Mantis items they own and send a notification when done. If there are issues found, move the item to Editor status and add a note explaining the issue, if no issues found leave unchanged, we will close these items after the cross-review.

 

. Cross review

DK will send assignments to everybody to review a chunk of Draft7. All: if an issue found, move the corresponding item to Editor status and add a note explaining the issue. Send a notification by email when the review has been completed.

 

. 1549 "add missing formal argument types"

The proposal requests to put the rewriting algorithm as an independent subclause F.x, while its description in the Draft7 was put under F.5 “Extended expressions”, though these items are not related.

 

Move (JH): Add a new subclause F.4 “Rewriting algorithms” and shift the numeration of the subsequent sections accordingly.

Second DB.

Passed by voice vote: 5y/0n/0a

 

. 1648 “Default reset for assertions”

 

Changes in the embedded assertion semantics (Mantis 2398) made the assertion a8 in the example at the end of 16.16 and the text following the example not relevant anymore. DK to send a letter to SV-SC with the request to fix this issue.

 

 

. 1667 “Local variable arguments for sequences and properties”

 

Mantis 2434 has eliminated the capability for default actual arguments to reference formal arguments. Therefore the rewriting algorithm steps describing property/sequence flattening need to be updated. JH to open a new Mantis item with the algorithm update request.

 

. 1668 “Local variable initializers”

 

Bug notes from the Draft6 review haven’t been implemented in Draft7. DK to open a new Mantis item requesting these changes.

 

. 1698 “The description of sampled value functions is insufficient”

 

“ev iff expression2” is an SV expression and should not have been changed to “ev if, and only if, expression2”. JH to add a bug note and to send an email to Stu explaining the requested changes.

 

. 2173 “The description of sampled value functions is insufficient”

 

F.3.4.6, the placement of the sentence beginning "Where specify(b) is ..." is not appropriate. JH to open a new Mantis item.

 

 

. 2478 “Clock flow subclause is not consistent with multiclocked property definition”

 

This is a new Mantis item suggesting removing the inconsistent description in 16.14.3 “Clock flow”.

JH: Need to make sure that the examples in the text to be removed are redundant. Otherwise the examples should be kept, but the text should be modified.

 

 

. 2450 “Derived syntax for restrict assertion statement”

 

clocking_event in Annex F should be typeset in italic. DK to add a bug note.

 

 

  • Editor question at the beginning of 14.14: “Is the term “entire

elaborated SystemVerilog model” defined?”

 

Answer: the elaboration model is defined in 3.12 and 23.10.4, and it is referenced in 20.10 as well. “Entire” is not a technical term here, but an English adjective to emphasize that the whole elaboration model should be considered.

 

 

  • The order of subclauses F.3.4.6 and F.3.4.7

 

Need to swap the subclauses since “Other operators” should be the last in the series. DK to open a new Mantis items. JH: make sure that all cross-references are updated.

 

 

 

Opens.

 

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